1. Field of the Invention
The present invention relates to a single-gate non-volatile memory and an operation method thereof, particularly to a super low-cost non-volatile memory with a single gate-source common terminal and an operation method thereof.
2. Description of the Related Art
The CMOS (Complementary Metal Oxide Semiconductor) process has been a normal fabrication method for ASIC (Application Specific Integrated Circuit). EEPROM (Electrically Erasable Programmable Read Only Memory), which features electric programmability and erasability and would not lose its memory after power is turned off, has been one of the popular non-volatile memories in the computer and information age.
A non-volatile memory is programmed via keeping charges to vary the gate voltage of the transistor thereof, or not keeping charges to preserve the gate voltage of the transistor. For a non-volatile memory, an erasion operation is to eliminate all the charges kept in the non-volatile memory and restore all the transistors to have the original gate voltages. In the conventional single-gate non-volatile memory, the gate, source and drain are respectively operated by independent voltages. Therefore, the conventional single-gate non-volatile memory has larger area and higher fabrication cost.
Accordingly, the present invention proposes a super low-cost non-volatile memory with a single gate-source common terminal and an operation method thereof to overcome the abovementioned problems, greatly decrease the area of a single-gate non-volatile memory and effectively increase the product value of the single-gate non-volatile memory.